1. Field of the Invention
The present invention generally relates to semiconductor devices and manufacturing methods of the same, and more specifically, to a semiconductor device wherein plural semiconductor elements are stacked on a wiring board and a manufacturing method of the semiconductor device.
2. Description of the Related Art
A chip stacked type semiconductor device which may be called a stacked package is known. In the chip stacked type semiconductor device, plural semiconductor chips (semiconductor elements) having different functions or plural semiconductor chips (semiconductor elements) having the same functions are stacked on a wiring board or a die pad of a lead frame. Each of electrode pads of the semiconductor chips and a bonding pad on the wiring board or an inner lead of the lead frame, are connected to each other by a bonding wire. Alternatively, the bonding wire connects the electrode pads to each other.
In this structure, since plural semiconductor chips are provided in a single semiconductor device, it is possible to respond to requests for an electronic device such as having multiple functions of the semiconductor device or a large capacity memory.
On the other hand, in a small size electronic device such as a mobile phone or a digital camera, a thin size or high density arrangement semiconductor device provided in the electronic device has been recently in demand.
A structure of a first example of a related art chip stacked type semiconductor device is shown in FIG. 1. FIG. 1(a) shows a cross section taken along line X-X′ of FIG. 1(b) that is a plan view. In FIG. 1(b), illustration of a sealing resin 10 is omitted.
In the chip stacked type semiconductor device 1, a first semiconductor chip 4 is provided on a wiring board 3 via a first adhesive 5. The wiring board has a main surface where plural outside connection terminals 2 are formed. In addition, a second semiconductor chip 6 is provided on the first semiconductor chip 4 via a second adhesive 7.
The second semiconductor chip 6 is smaller than the first semiconductor chip 4. The first semiconductor chip 4 and the second semiconductor chip 6 are provided in a so-called facing up state where electronic circuit forming surfaces (main surfaces) of the first semiconductor chip 4 and the second semiconductor chip 6 do not face toward the wiring board 3. Outside connection electrode pads (not illustrated in FIG. 1) of the first semiconductor chip 4 and the second semiconductor chip 6 are provided on the main surfaces of the first semiconductor chip 4 and the second semiconductor chip 6.
The electrode pads of the first semiconductor chip 4 and the second semiconductor chip 6 and bonding pads (not illustrated in FIG. 1) on the wiring board 3 are connected to each other by bonding wires 8 and 9, respectively. The first semiconductor chip 4 and the second semiconductor chip 6 together with the bonding wires 8 and 9 are sealed on the wiring board 3 by sealing resin 10.
However, in the structure shown in FIG. 1, it is not possible to stack semiconductor chips having the same chip sizes. Therefore, freedom degree for designing combinations of the semiconductor chips stacked on the wiring board 3 is low.
Because of this, in order to improve the design freedom degree of combination of the semiconductor chips stacked on the wiring board, structures shown in FIG. 2 through FIG. 4 have been suggested. In FIG. 2 through FIG. 4, parts that are the same as the parts shown in FIG. 1 are given the same reference numerals, and explanation thereof is omitted.
An example of another related art chip stacked type semiconductor device is shown in FIG. 2. FIG. 2(a) shows a cross section seen in a direction indicated by an arrow Y in FIG. 2(b) that is a plan view. In FIG. 2(b), illustration of a sealing resin 10 is omitted.
In the chip stacked type semiconductor device 11, a first semiconductor chip 14 is provided on the wiring board 3 via the first adhesive 5. In addition, a second semiconductor chip 16 is provided on the first semiconductor chip 14 via the second adhesive 7.
The first semiconductor chip 14 and the second semiconductor chip 16 have rectangular-shaped configurations. The semiconductor chip 16 is provided on the first semiconductor chip 14 so that the first semiconductor chip 14 and the second semiconductor chip 16 cross each other. Electrode pads (not illustrated in FIG. 2) are provided at short side end parts facing each other on main surfaces of the first semiconductor chip 14 and the second semiconductor chip 16 and connected to bonding pads (not illustrated in FIG. 2) provided on the wiring board 3 via the bonding wires 8 and 9.
The first semiconductor chip 14 and the second semiconductor chip 16 together with the bonding wires 8 and 9 are sealed on the wiring board 3 by sealing resin 10. See, for example, Japanese Laid-Open Patent Application Publication No. 2-312265.
An example of another related art chip stacked type semiconductor device is shown in FIG. 3. FIG. 3(a) shows a cross section taken along line X-X′ of FIG. 3(b) that is a plan view. In FIG. 3(b), illustration of a sealing resin 10 is omitted.
In the chip stacked type semiconductor device 21, a first semiconductor chip 24 is provided on the wiring board 3 in a so-called face down (flip chip) state where an electronic circuit forming surface (main surface) of the first semiconductor chip 24 faces the wiring board 3. In addition, a second semiconductor chip 26 is provided on the first semiconductor chip 24 via the second adhesive 7 where an electronic circuit forming surface (main surface) of the second semiconductor chip 26 faces upward.
Gold (Au) bumps 22 are formed on the electrode pads (not illustrated in FIG. 3) of the first semiconductor chip 24. The gold (Au) bumps 22 of the first semiconductor chip 24 are connected to the bonding pads (not illustrated in FIG. 3) of the wiring board 3. An underfill material 23 fills in between the first semiconductor chip 24 and the wiring board 3.
On the other hand, the electrode pads of the second semiconductor chip 26 and the bonding pads on the wiring board 3 are connected to each other by the bonding wires 9. In addition, the first semiconductor chip 24 and the second semiconductor chip 26 together with the bonding wires 9 are sealed on the wiring board 3 by sealing resin 10. See, for example, Japanese Laid-Open Patent Application Publication No. 3-255657.
In this structure as compared to the structures shown in FIG. 1 and FIG. 2, since there is less limitation of sizes and configurations of the stacked semiconductor chips, the design freedom degree of the combination of the semiconductor chips is high.
An example of another related art chip stacked type semiconductor device is shown in FIG. 4. FIG. 4(a) shows a cross section taken along line X-X′ of FIG. 4(b) that is a plan view. In FIG. 4(b), illustration of a sealing resin 10 is omitted.
In the chip stacked type semiconductor device 31, a first semiconductor chip 34 is provided on the wiring board 3 via the first adhesive 5. In addition, a second semiconductor chip 36 is provided on the first semiconductor chip 34 via the second adhesive 37 and is shifted against the first semiconductor chip 34.
Electrode pads (not illustrated in FIG. 4) provided at end parts of electronic circuit forming surfaces (main surfaces) of the first semiconductor chip 34 and the second semiconductor chip 36 are connected to the bonding pads (not illustrated in FIG. 4) on the wiring board 3 via the bonding wires 8 and 9, respectively. In addition, the first semiconductor chip 34 and the second semiconductor chip 36 together with the bonding wires 8 and 9 are sealed on the wiring board 3 by sealing resin 10. See, for example, Japanese Laid-Open Patent Application Publication No. 6-224362.
However, in the related art cases shown in FIG. 1 through FIG. 4, the second semiconductor chips 6, 26, 26, and 36 situated at upper steps and the corresponding wiring boards 3 are connected to each other by the corresponding bonding wires 9.
Because of this, it is necessary to provide the sealing resin 10 for parts corresponding to the heights of wire loops of the bonding wires 9, namely parts corresponding to height a from upper surfaces of the second semiconductor chips 6, 26, 26, and 36 in the structures shown in FIG. 1 through FIG. 4. Accordingly, in these structures, it is difficult to respond to the request for making the semiconductor device thin.
On the other hand, it may be undertaken to make the semiconductor chips thin in response to the demand for making the semiconductor device thin. However, if the semiconductor chips are made thin, the yield rate may be reduced due to degradation of the strength of the semiconductor chip or reliability of the semiconductor device may be reduced. Furthermore, manufacturing costs may be increased due to addition of manufacturing steps for making the semiconductor device thin.